Xilinx, Inc

Makers of Spartan, Virtex, Hardwire and X lines CPLDs.

available from DigiKey Corp
comparison matrix
Spartain Series
Cores available for ASIC replacement by FPGA's
Software manuals online
Xess Prototyping boards

PROGRAMMABLE PRODUCT FAMILY OVERVIEW
Industry Category	Product Series	Technology	Ideal Use	Series Key Features	Product Family	Macrocells/ Logic Cells	Max. Logic Gates	Max. I/O	Voltage
Complex PLD (CPLDs)	XC9000	FLASH	ISP Predictable Timing Fast Pin-to-Pin Speeds	5V ISP, 5ns Tpd, JTAG, Industry-leading Pin-locking, High Endurance, Free HDL to JEDEC via WebFITTER	XC9500	36-288	0.8K-6.4K	192	5V
Reprogrammable FPGAs	XC4000 pinouts	SRAM	High Density High Performance	Select-RAM^™ Distributed RAM, Dedicated Arithmetic Logic, PCI Compliant, JTAG, Internal 3-State buffers	XC4000E	238-2,432	3K-25K	256	5V
					XC4000EX	2,432-3,078	28K-36K	288	5V
					XC4000XL	466-7,448	5K-85K	448	3.3V
					XC4000XV	10,982	125K	448	2.5V
	Spartan Series	SRAM	Low Cost High Performance		XCS05	238	3K-20K	205	5V
					XCS10	466
					XCS20	950
					XCS30	1,368
					XCS40	1,862

see also:

XESS Corp FPGA examples and solutions
www.fliptronics.com
Using Three-State Enable Registers in XLA, XV, and SpartanXL FPGAs. The support for this feature is much better in the Virtex parts.

file: /Techref/xilinx/index.htm, 7KB, , updated: 2002/11/1 18:08, local time: 2024/11/21 10:54,

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