SX Watchdog Timer

Stephen C. Holland Says:

Wherever you put the CLR !WDT instruction in your main loop, you need to make sure you can get there before the watchdog timer will overflow.

The documentation of the watchdog in the Ubicom/Scenix datasheets is really weak. Basically, the watchdog runs from it's own internal oscillator which runs at ~14KHz, or a period of 714us. Ath this rate, the 8-bit counter counts from 0x00 to 0xFF in 18ms. This amount of time is the default watchdog timeout period. The watchdog timeout can be increased by using the 8-bit prescaler register, as long as you are not already using it for the RTCC. You can assign the prescaler to the RTCC or watchdog by controlling the PSA bit in the OPTION register. The prescaler is then configured with the PS[2:0] bits in the OPTION register.The watchdog can also run in power down mode. In your reset software, you can then look at the TO bit to see if a watchdog timeout occured. You may want to have some different initialization if the watchdog occurs.

I have attached some code I wrote awhile back to check for all forms of reset in the reset vector. It's a little old, and may contain some errors (it was written when an older version of SASM was around) With this, you can know if you are in the reset vector because of power up or MCLR, watchdog timeout, or MIWU (from sleep mode). You could extend the power-up/MCLR code to actually test for the presence of some software-initialized RAM locations to tell between an MCLR and power-up condition. The reason for this is that the RAM comes up at unkown values on power-up, but would remain the same as whatever they were last set to on an MCLR. This is a similiar approach used in your car radio so that it keeps it's presets after it powers up.

Code:

• ;*****************************************************************************************
  ; Copyright © [01/26/1999] Scenix Semiconductor, Inc. All rights reserved.
  ;
  ; Scenix Semiconductor, Inc. assumes no responsibility or liability for
  ; the use of this [product, application, software, any of these products].
  ; Scenix Semiconductor conveys no license, implicitly or otherwise, under
  ; any intellectual property rights.
  ; Information contained in this publication regarding (e.g.: application,
  ; implementation) and the like is intended through suggestion only and may
  ; be superseded by updates. Scenix Semiconductor makes no representation
  ; or warranties with respect to the accuracy or use of these information,
  ; or infringement of patents arising from such use or otherwise.
  ;*****************************************************************************************
  ; 
  ; Filename:	
  ;
  ; Authors:	
  ;		
  ;		
  ;
  ; Revision:	1.00
  ;
  ; Part:		SX28AC datecode 9929AA
  ; Freq:		50Mhz
  ; Compiled using Parallax SX-Key software v1.07 and SASM 1.40
  ;
  ; Date Written: 
  ;
  ; Last Revised: 
  ;
  ; Program Description:
  ;
  ;	
  ;
  ; Revision History:
  ;
  ;*****************************************************************************************
  
  ;*****************************************************************************************
  ; Target SX
  ; Uncomment one of the following lines to choose the SX18AC, SX20AC, SX28AC, SX48BD/ES,
  ; SX48BD, SX52BD/ES or SX52BD. For SX48BD/ES and SX52BD/ES, uncomment both defines,
  ; SX48_52 and SX48_52_ES.
  ;*****************************************************************************************
  ;SX18_20
  SX28
  ;SX48_52
  ;SX48_52_ES
  
  ;*****************************************************************************************
  ; Assembler Used
  ; Uncomment the following line if using the Parallax SX-Key assembler. SASM assembler
  ; enabled by default.
  ;*****************************************************************************************
  ;SX_Key
  
  	;*********************************************************************************
  	; Assembler directives:
  	;	high speed external osc, turbo mode, 8-level stack, and extended option reg.
  	;
  	;	SX18/20/28 - 4 pages of program memory and 8 banks of RAM enabled by default.
  	;	SX48/52 - 8 pages of program memory and 16 banks of RAM enabled by default.
  	;                
  	;*********************************************************************************
  
  IFDEF SX_Key 				;SX-Key Directives
    IFDEF SX18_20				;SX18AC or SX20AC device directives for SX-Key
  		device	SX18L,oscxt4,turbo,stackx_optionx
    ENDIF
    IFDEF SX28				;SX28AC device directives for SX-Key		
  		device	SX28L,oschs2,turbo,stackx_optionx,watchdog
    ENDIF
    IFDEF SX48_52_ES			;SX48BD/ES or SX52BD/ES device directives for SX-Key
  		device	oschs,turbo,stackx,optionx
    ELSE
      IFDEF SX48_52				;SX48/52/BD device directives for SX-Key
  		device	oschs2
      ENDIF
    ENDIF
  		freq	1_000_000
  ELSE  					;SASM Directives
    IFDEF SX18_20				;SX18AC or SX20AC device directives for SASM
  		device	SX18,oschs2,turbo,stackx,optionx
    ENDIF
    IFDEF SX28				;SX28AC device directives for SASM
  		device	SX28,oschs2,turbo,stackx,optionx
    ENDIF
    IFDEF SX48_52_ES			;SX48BD/ES or SX52BD/ES device directives for SASM
  		device	SX52,oschs,turbo,stackx,optionx
    ELSE
      IFDEF SX48_52			;SX48BD or SX52BD device directives for SASM
  		device	SX52,oschs2   
      ENDIF
    ENDIF
  ENDIF
  		id	'  '			;
  		reset	reset_entry		; set reset vector
  
  ;*****************************************************************************************
  ; Macros
  ;*****************************************************************************************
  
  	;*********************************************************************************
  	; Macro: _bank
  	; Sets the bank appropriately for all revisions of SX.
  	;
  	; This is required since the bank instruction has only a 3-bit operand, it cannot
  	; be used to access all 16 banks of the SX48/52. For this reason FSR.4 (for SX48/52BD/ES)
  	; or FSR.7 (SX48/52bd production release) needs to be set appropriately, depending
  	; on the bank address being accessed. This macro fixes this.
  	;
  	; So, instead of using the bank instruction to switch between banks, use _bank instead.
  	; 
  	;*********************************************************************************
  _bank	macro	1
    noexpand
  	bank	\1
  	IFDEF SX48_52
  	  IFDEF SX48_52_ES
  	    IF \1 & %00010000		;SX48BD/ES and SX52BD/ES (engineering sample) bank instruction
    expand
  		setb	fsr.4		;modifies FSR bits 5,6 and 7. FSR.4 needs to be set by software.
    noexpand
  	    ENDIF
  	  ELSE
  	    IF \1 & %10000000		;SX48BD and SX52BD (production release) bank instruction 
    expand
  		setb	fsr.7		;modifies FSR bits 4,5 and 6. FSR.7 needs to be set by software.
    noexpand
  	    ELSE
    expand
  		clrb	fsr.7
    noexpand
  	    ENDIF
  	  ENDIF
  	ENDIF
  	endm
  
  	;*********************************************************************************
  	; Macro: _mode
  	; Sets the MODE register appropriately for all revisions of SX.
  	;
  	; This is required since the MODE (or MOV M,#) instruction has only a 4-bit operand. 
  	; The SX18/20/28AC use only 4 bits of the MODE register, however the SX48/52BD have 
  	; the added ability of reading or writing some of the MODE registers, and therefore use
  	; 5-bits of the MODE register. The  MOV M,W instruction modifies all 8-bits of the 
  	; MODE register, so this instruction must be used on the SX48/52BD to make sure the MODE
  	; register is written with the correct value. This macro fixes this.
  	;
  	; So, instead of using the MODE or MOV M,# instructions to load the M register, use
  	;  _mode instead.
  	; 
  	;*********************************************************************************
  _mode	macro	1
    noexpand
  	IFDEF SX48_52
    expand
  		mov	w,#\1&$1F	;loads the M register correctly for the SX48BD and SX52BD
  		mov	m,w
    noexpand
  	ELSE
    expand
  		mov	m,#\1&$0F	;loads the M register correctly for the SX18AC, SX20AC
  					;and SX28AC
    noexpand
  	ENDIF
  	endm
  
  ;*****************************************************************************************
  ; Data Memory address definitions
  ; These definitions ensure the proper address is used for banks 0 - 7 for 2K SX devices
  ; (SX18/20/28) and 4K SX devices (SX48/52). 
  ;*****************************************************************************************
  IFDEF SX48_52
  
  global_org	=	$0A
  bank0_org	=	$00
  bank1_org	=	$10
  bank2_org	=	$20
  bank3_org	=	$30
  bank4_org	=	$40
  bank5_org	=	$50
  bank6_org	=	$60
  bank7_org	=	$70
  
  ELSE
  
  global_org	=	$08
  bank0_org	=	$10
  bank1_org	=	$30
  bank2_org	=	$50
  bank3_org	=	$70
  bank4_org	=	$90
  bank5_org	=	$B0
  bank6_org	=	$D0
  bank7_org	=	$F0
  
  ENDIF
  ;*****************************************************************************************
  ; Global Register definitions
  ; NOTE: Global data memory starts at $0A on SX48/52 and $08 on SX18/20/28.
  ;*****************************************************************************************
  		org     global_org
  
  global_temp	equ	global_org+0
  function_temp	equ	global_org+1
  
  portb_buff	equ	global_org+5
  
  flags		equ	global_org+6
    mclr_detected		equ	flags.0
    wdt_detected		equ	flags.1
    miwu_detected		equ	flags.2
  
  ;*****************************************************************************************
  ; RAM Bank Register definitions
  ;*****************************************************************************************
  
  	;*********************************************************************************
  	; Bank 0
  	;*********************************************************************************
  		org     bank0_org
  
  bank0		=	$
  
  
  	;*********************************************************************************
  	; Bank 1
  	;*********************************************************************************
  		org     bank1_org
  
  bank1		=	$
  
  
  	;*********************************************************************************
  	; Bank 2
  	;*********************************************************************************
  		org     bank2_org
  
  bank2		=	$
  
  
  	;*********************************************************************************
  	; Bank 3
  	;*********************************************************************************
  		org     bank3_org
  
  bank3		=	$
  
  
  	;*********************************************************************************
  	; Bank 4
  	;*********************************************************************************
  		org     bank4_org
  
  bank4		=	$
  
  
  	;*********************************************************************************
  	; Bank 5
  	;*********************************************************************************
  		org     bank5_org
  
  bank5		=	$
  
  
  	;*********************************************************************************
  	; Bank 6
  	;*********************************************************************************
  		org     bank6_org
  
  bank6		=	$
  
  
  	;*********************************************************************************
  	; Bank 7
  	;*********************************************************************************
  		org     bank7_org
  
  bank7		=	$
  
  
  IFDEF SX48_52
  	;*********************************************************************************
  	; Bank 8
  	;*********************************************************************************
  		org	$80	;bank 8 address on SX52
  
  bank8		=	$
  
  
  	;*********************************************************************************
  	; Bank 9
  	;*********************************************************************************
  		org	$90	;bank 9 address on SX52
  
  bank9		=	$
  
  
  	;*********************************************************************************
  	; Bank A
  	;*********************************************************************************
  		org	$A0	;bank A address on SX52
  
  bankA		=	$
  
  
  	;*********************************************************************************
  	; Bank B
  	;*********************************************************************************
  		org	$B0	;bank B address on SX52
  
  bankB		=	$
  
  
  	;*********************************************************************************
  	; Bank C
  	;*********************************************************************************
  		org	$C0	;bank C address on SX52
  
  bankC		=	$
  
  
  	;*********************************************************************************
  	; Bank D
  	;*********************************************************************************
  		org	$D0	;bank D address on SX52
  
  bankD		=	$
  
  
  	;*********************************************************************************
  	; Bank E
  	;*********************************************************************************
  		org	$E0	;bank E address on SX52
  
  bankE		=	$
  
  
  	;*********************************************************************************
  	; Bank F
  	;*********************************************************************************
  		org	$F0	;bank F address on SX52
  
  bankF		=	$
  
  
  ENDIF
  ;*****************************************************************************************
  ; Port Assignment
  ;*****************************************************************************************
  
  RA_latch	equ	%00000000		;SX18/20/28/48/52 port A latch init
  RA_DDIR		equ	%11111111		;SX18/20/28/48/52 port A DDIR value
  RA_LVL		equ	%00000000		;SX18/20/28/48/52 port A LVL value
  RA_PLP		equ	%00000000
  
  RB_latch	equ	%00001000		;SX18/20/28/48/52 port B latch init
  RB_DDIR		equ	%11110111		;SX18/20/28/48/52 port B DDIR value
  RB_ST		equ	%11111111		;SX18/20/28/48/52 port B ST value
  RB_LVL		equ	%00000000		;SX18/20/28/48/52 port B LVL value
  RB_PLP		equ	%00001000		;SX18/20/28/48/52 port B PLP value
  
  RB_edge		equ	%11111111		;SX18/20/28/48/52 port B interrupt edges
  RB_int		equ	%11111110		;SX18/20/28/48/52 port B interrupt enable
  
  RC_latch	equ	%00000000		;SX18/20/28/48/52 port C latch init
  RC_DDIR		equ	%11111110		;SX18/20/28/48/52 port C DDIR value
  RC_ST		equ	%11111111		;SX18/20/28/48/52 port C ST value
  RC_LVL		equ	%00000000		;SX18/20/28/48/52 port C LVL value
  RC_PLP		equ	%00000000		;SX18/20/28/48/52 port C PLP value
  		
  IFDEF SX48_52	;SX48BD/52BD Port initialization values
  RD_latch	equ	%00000000		;SX48/52 port D latch init
  RD_DDIR		equ	%11111111		;SX48/52 port D DDIR value
  RD_ST		equ	%11111111		;SX48/52 port D ST value
  RD_LVL		equ	%00000000		;SX48/52 port D LVL value
  RD_PLP		equ	%00000000		;SX48/52 port D PLP value
  
  RE_latch	equ	%00000000		;SX48/52 port E latch init
  RE_DDIR		equ	%11111111		;SX48/52 port E DDIR value
  RE_ST		equ	%11111111		;SX48/52 port E ST value
  RE_LVL		equ	%00000000		;SX48/52 port E LVL value
  RE_PLP		equ	%00000000		;SX48/52 port E PLP value
  ENDIF
  	;*********************************************************************************
  	; Pin Definitions
  	;*********************************************************************************
  
  
  ;*****************************************************************************************
  ; Program constants
  ;*****************************************************************************************
  
  int_period	equ	217		;RTCC Interrupt rate
  
  IFDEF SX48_52
  	;*********************************************************************************
  	; SX48BD/52BD Mode addresses
  	; *On SX48BD/52BD, most registers addressed via mode are read and write, with the
  	; exception of CMP and WKPND which do an exchange with W.
  	;*********************************************************************************
  ; Timer (read) addresses
  TCPL_R		equ	$00		;Read Timer Capture register low byte
  TCPH_R		equ	$01		;Read Timer Capture register high byte
  TR2CML_R	equ	$02		;Read Timer R2 low byte
  TR2CMH_R	equ	$03		;Read Timer R2 high byte
  TR1CML_R	equ	$04		;Read Timer R1 low byte
  TR1CMH_R	equ	$05 		;Read Timer R1 high byte
  TCNTB_R		equ	$06		;Read Timer control register B
  TCNTA_R		equ	$07		;Read Timer control register A
  
  ; Exchange addresses
  CMP		equ	$08		;Exchange Comparator enable/status register with W
  WKPND		equ	$09		;Exchange MIWU/RB Interrupts pending with W
  
  ; Port setup (read) addresses
  ST_R		equ	$0C		;Read Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
  LVL_R		equ	$0D		;Read Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
  PLP_R		equ	$0E		;Read Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
  DDIR_R		equ	$0F		;Read Port Direction, 0 = output, 1 = input
  
  ; Timer (write) addresses
  CLR_TMR		equ	$10		;Resets 16-bit Timer
  TR2CML_W	equ	$12		;Write Timer R2 low byte
  TR2CMH_W	equ	$13		;Write Timer R2 high byte
  TR1CML_W	equ	$14		;Write Timer R1 low byte
  TR1CMH_W	equ	$15 		;Write Timer R1 high byte
  TCNTB_W		equ	$16		;Write Timer control register B
  TCNTA_W		equ	$17		;Write Timer control register A
  
  ; Interrupt setup addresses
  WKED_W		equ	$1A		;Write MIWU/RB Interrupt edge setup, 0 = falling, 1 = rising
  WKEN_W		equ	$1B		;Write MIWU/RB Interrupt edge setup, 0 = enabled, 1 = disabled
  
  ; Port setup (write) addresses
  ST_W		equ	$1C		;Write Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
  LVL_W		equ	$1D		;Write Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
  PLP_W		equ	$1E		;Write Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
  DDIR_W		equ	$1F		;Write Port Direction, 0 = output, 1 = input
  
  ELSE
  
  	;*********************************************************************************
  	; SX18AC/20AC/28AC Mode addresses
  	; *On SX18/20/28, all registers addressed via mode are write only, with the exception of
  	; CMP and WKPND which do an exchange with W.
  	;*********************************************************************************
  ; Exchange addresses
  CMP		equ	$08		;Exchange Comparator enable/status register with W
  WKPND		equ	$09		;Exchange MIWU/RB Interrupts pending with W
  
  ; Interrupt setup addresses
  WKED_W		equ	$0A		;Write MIWU/RB Interrupt edge setup, 0 = falling, 1 = rising
  WKEN_W		equ	$0B		;Write MIWU/RB Interrupt edge setup, 0 = enabled, 1 = disabled
  
  ; Port setup (write) addresses
  ST_W		equ	$0C		;Write Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
  LVL_W		equ	$0D		;Write Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
  PLP_W		equ	$0E		;Write Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
  DDIR_W		equ	$0F		;Write Port Direction
  
  ENDIF
  
  ;*****************************************************************************************
  ; Interrupt Service Routine
  ;*****************************************************************************************
  ; Note: The interrupt code must always originate at address $0.
  ;
  ; Interrupt Frequency = (Cycle Frequency / -(retiw value))  For example:
  ; With a retiw value of -217 and an oscillator frequency of 50MHz, this
  ; code runs every 4.34us.
  ;*****************************************************************************************
  		org     $0
  interrupt					;3
  		_mode	WKPND			;point MODE to swap WKPND register
  		clr     w	         	;Clear WKPND_B register
  		mov     !rb,w	         	;Get pending RB interrupts
  
  		xor	portb_buff,#%01000000
  
  interrupt_out
  		reti
  
  
  	;*********************************************************************************
  	; Virtual Peripheral: 
  	;
  	;
  	;	Input variable(s): 
  	;	Output variable(s): 
  	;	Variable(s) affected: 
  	;	Flag(s) affected: 
  	;*********************************************************************************
  label
  
  
  
  	;*********************************************************************************
  	; Set Interrupt Rate
  	;*********************************************************************************
  isr_end		mov	w,#-int_period		;refresh RTCC on return
  		retiw				;return from the interrupt
  						; = 1/(int_period*RTCC prescaler*1/50MHz)
  						; = 1/(217*1*20ns) = 4.34us
  ;*****************************************************************************************
  ; End of the Interrupt Service Routine
  ;*****************************************************************************************
  
  
  ;*****************************************************************************************
  ; RESET VECTOR 
  ;*****************************************************************************************
  
  	;*********************************************************************************
  	; Program execution begins here on power-up or after a reset
  	;*********************************************************************************
  	org	$400
  reset_entry		
  	;*********************************************************************************
  	; Initialise port direction (always reset to default of $FF on MIWU, WDT, MCLR)
  	;*********************************************************************************
  		_mode	DDIR_W			;point MODE to write DDIR register
  		mov	w,#RA_DDIR		;Setup RA Direction register, 0 = output, 1 = input		
  		mov	!ra,w	
  		mov	w,#RB_DDIR		;Setup RB Direction register, 0 = output, 1 = input
  		mov	!rb,w			
  		mov	w,#RC_DDIR		;Setup RC Direction register, 0 = output, 1 = input
  		mov	!rc,w			
  IFDEF SX48_52
  		mov	w,#RD_DDIR		;Setup RD Direction register, 0 = output, 1 = input
  		mov	!rd,w			
  		mov	w,#RE_DDIR		;Setup RE Direction register, 0 = output, 1 = input
  		mov	!re,w			
  ENDIF
  	;*********************************************************************************
  	; Check for reset condition
  	;*********************************************************************************
  		sb	TO			;did watchdog timeout occur?
  		jmp	wd_to			;yes, else skip
  		sb	PD			;did MIWU occur?
  		jmp	miwu			;yes, else skip
  
  ;************************************
  power_up_mclr	;power up or mclr occured
  		setb	mclr_detected
  
  		_mode	WKPND			;point MODE to swap WKPND register
  		clr     w	         	;Clear WKPND_B register
  		mov     !rb,w	         	;Get pending RB interrupts
  	;*********************************************************************************
  	; Initialise all port configuration
  	;*********************************************************************************
  
  		_mode	ST_W			;point MODE to write ST register
  		mov     w,#RB_ST            	;Setup RB Schmitt Trigger, 0 = enabled, 1 = disabled
  		mov	!rb,w		
  		mov     w,#RC_ST            	;Setup RC Schmitt Trigger, 0 = enabled, 1 = disabled
  		mov	!rc,w	
  IFDEF SX48_52
  		mov     w,#RD_ST            	;Setup RD Schmitt Trigger, 0 = enabled, 1 = disabled
  		mov	!rd,w		
  		mov     w,#RE_ST            	;Setup RE Schmitt Trigger, 0 = enabled, 1 = disabled
  		mov	!re,w		
  ENDIF
  		_mode	LVL_W			;point MODE to write LVL register
  		mov     w,#RA_LVL            	;Setup RA CMOS or TTL levels, 0 = TTL, 1 = CMOS
  		mov	!ra,w		 
  		mov     w,#RB_LVL            	;Setup RB CMOS or TTL levels, 0 = TTL, 1 = CMOS
  		mov	!rb,w		
  		mov     w,#RC_LVL            	;Setup RC CMOS or TTL levels, 0 = TTL, 1 = CMOS
  		mov	!rc,w	
  IFDEF SX48_52
  		mov     w,#RD_LVL            	;Setup RD CMOS or TTL levels, 0 = TTL, 1 = CMOS
  		mov	!rd,w		
  		mov     w,#RE_LVL            	;Setup RE CMOS or TTL levels, 0 = TTL, 1 = CMOS
  		mov	!re,w		
  ENDIF
  		_mode	PLP_W			;point MODE to write PLP register
  		mov     w,#RA_PLP            	;Setup RA Weak Pull-up, 0 = enabled, 1 = disabled
  		mov	!ra,w		 
  		mov     w,#RB_PLP            	;Setup RB Weak Pull-up, 0 = enabled, 1 = disabled
  		mov	!rb,w		
  		mov     w,#RC_PLP            	;Setup RC Weak Pull-up, 0 = enabled, 1 = disabled
  		mov	!rc,w	
  IFDEF SX48_52
  		mov     w,#RD_PLP            	;Setup RD Weak Pull-up, 0 = enabled, 1 = disabled
  		mov	!rd,w		
  		mov     w,#RE_PLP            	;Setup RE Weak Pull-up, 0 = enabled, 1 = disabled
  		mov	!re,w		
  ENDIF
  		mov     w,#RA_latch          	;Initialize RA data latch
  		mov     ra,w		
  		mov     w,#RB_latch         	;Initialize RB data latch
  		mov     rb,w		
  		mov     w,#RC_latch          	;Initialize RC data latch
  		mov     rc,w		
  IFDEF SX48_52
  		mov     w,#RD_latch         	;Initialize RD data latch
  		mov     rd,w			
  		mov     w,#RE_latch         	;Initialize RE data latch
  		mov     re,w			
  ENDIF
  
  	;*********************************************************************************
  	; Clear all Data RAM locations
  	;*********************************************************************************
  IFDEF SX48_52   				;SX48/52 RAM clear routine
  		mov	w,#$0a			;reset all ram starting at $0A
  		mov	fsr,w
  :zero_ram	clr	ind			;clear using indirect addressing
  		incsz	fsr			;repeat until done
  		jmp	:zero_ram
  
  		_bank	bank0			;clear bank 0 registers
  		clr	$10
  		clr	$11
  		clr	$12
  		clr	$13
  		clr	$14
  		clr	$15
  		clr	$16
  		clr	$17
  		clr	$18
  		clr	$19
  		clr	$1a
  		clr	$1b
  		clr	$1c
  		clr	$1d
  		clr	$1e
  		clr	$1f
  
  ELSE     					;SX18/20/28 RAM clear routine
  		clr	fsr			;reset all ram banks
  :zero_ram	sb	fsr.4			;are we on low half of bank?
  		setb	fsr.3			;If so, don't touch regs 0-7
  		clr	ind			;clear using indirect addressing
  		incsz	fsr			;repeat until done
  		jmp	:zero_ram
  ENDIF
  
  	;	_mode	WKPND			;point MODE to swap WKPND register
  	;	clr     w	         	;Clear WKPND_B register
  	;	mov     !rb,w	         	;Get pending RB interrupts
  	;	_mode	WKED_W			;point MODE to write WKED_B register
  	;	mov     w,#RB_edge         	;Initialize RB interrupt edges
  	;	mov     !rb,w		
  	;	_mode	WKEN_W			;point MODE to write WKEN_B register
  	;	mov     w,#RB_int         	;Enable/Disable RB interrupts
  	;	mov     !rb,w		
  
  		jmp	continue
  
  ;******************************************
  wd_to		;watchdog timeout occured
  		setb	wdt_detected
  
  	;	mov	w,#RB_DDIR		;Setup RB Direction register, 0 = output, 1 = input
  	;	mov	!rb,w			
  	;	mov	w,#RC_DDIR		;Setup RB Direction register, 0 = output, 1 = input
  	;	mov	!rc,w			
  
  	;	_mode	WKPND			;point MODE to swap WKPND register
  	;	clr     w	         	;Clear WKPND_B register
  	;	mov     !rb,w	         	;Get pending RB interrupts
  	;	_mode	WKED_W			;point MODE to write WKED_B register
  	;	mov     w,#RB_edge         	;Initialize RB interrupt edges
  	;	mov     !rb,w		
  	;	_mode	WKEN_W			;point MODE to write WKEN_B register
  	;	mov     w,#RB_int         	;Enable/Disable RB interrupts
  	;	mov     !rb,w		
  
  		xor	portb_buff,#%00001000
  		mov	rb,portb_buff
  
  		clr	!wdt			;reset TO and PD bits
  		jmp	continue
  
  ;************************************************
  miwu		setb	miwu_detected
  		clr	!wdt			;reset TO and PD bits
  	;	mov	w,#RB_DDIR		;Setup RB Direction register, 0 = output, 1 = input
  	;	mov	!rb,w			
  	;	_mode	WKED_W			;point MODE to write WKED_B register
  	;	mov     w,#RB_edge         	;Initialize RB interrupt edges
  	;	mov     !rb,w		
  	;	_mode	WKEN_W			;point MODE to write WKEN_B register
  	;	mov     w,#RB_int         	;Enable/Disable RB interrupts
  	;	mov     !rb,w		
  
  continue
  	;*********************************************************************************
  	; Initialize program/VP registers
  	;*********************************************************************************
  
  
  	;*********************************************************************************
  	; Setup and enable RTCC interrupt, WREG register, RTCC/WDT prescaler
  	;*********************************************************************************
  
  RTCC_ON		=	%10000000	;Enables RTCC at address $01 (RTW hi)
  					;*WREG at address $01 (RTW lo) by default
  RTCC_ID		=	%01000000	;Disables RTCC edge interrupt (RTE_IE hi)
  					;*RTCC edge interrupt (RTE_IE lo) enabled by default
  RTCC_INC_EXT	=	%00100000	;Sets RTCC increment on RTCC pin transition (RTS hi)
  					;*RTCC increment on internal instruction (RTS lo) is default
  RTCC_FE		=	%00010000	;Sets RTCC to increment on falling edge (RTE_ES hi)
  					;*RTCC to increment on rising edge (RTE_ES lo) is default
  RTCC_PS_ON	=	%00000000	;Assigns prescaler to RTCC (PSA lo)
  RTCC_PS_OFF	=	%00001000	;Assigns prescaler to WDT (PSA hi)
  PS_000		=	%00000000	;RTCC = 1:2, WDT = 1:1
  PS_001		=	%00000001	;RTCC = 1:4, WDT = 1:2
  PS_010		=	%00000010	;RTCC = 1:8, WDT = 1:4
  PS_011		=	%00000011	;RTCC = 1:16, WDT = 1:8
  PS_100		=	%00000100	;RTCC = 1:32, WDT = 1:16
  PS_101		=	%00000101	;RTCC = 1:64, WDT = 1:32
  PS_110		=	%00000110	;RTCC = 1:128, WDT = 1:64
  PS_111		=	%00000111	;RTCC = 1:256, WDT = 1:128
  
  		mov	w,#RTCC_PS_OFF | RTCC_ID | PS_111	;setup option register
  		mov	!option,w
  
  end_init	jmp	@main
  
  
  
  ;*****************************************************************************************
  ; MAIN PROGRAM CODE 
  ;*****************************************************************************************
  
  	;*********************************************************************************
  	; Main
  	;*********************************************************************************
  main		
  
  
  	;*********************************************************************************
  	; Main Program Loop
  	;*********************************************************************************
  main_loop
  		
  		sleep
  
  		jmp	main_loop
  
  
  org	$200
  ;*****************************************************************************************
  ; Jump table for page 1
  ; Enables CALLs to functions in the second half of the page 
  ;*****************************************************************************************
  function_label_2	jmp	function_label_2_
  
  ;*****************************************************************************************
  ; Subroutines
  ;*****************************************************************************************
  
  	;*********************************************************************************
  	; Function: 
  	; 
  	; Inputs:
  	;	
  	; Outputs:
  	;	
  	; Registers affected:
  	;
  	; Functions Called:
  	;
  	;*********************************************************************************
  function_label
  
  		retp
  
  	;*********************************************************************************
  	; Function: 
  	; 
  	; Inputs:
  	;	
  	; Outputs:
  	;	
  	; Registers affected:
  	;
  	; Functions Called:
  	;
  	;*********************************************************************************
  function_label_1
  
  		retp
  
  	;*********************************************************************************
  	; Function: 
  	; 
  	; Inputs:
  	;	
  	; Outputs:
  	;	
  	; Registers affected:
  	;
  	; Functions Called:
  	;
  	;*********************************************************************************
  function_label_2_
  
  		retp
  
  ;*****************************************************************************************
  END		;End of program code
  ;*****************************************************************************************
  

  +

  .